1. Field of the Invention
The present invention relates to a band-pass ΔΣ AD modulator for AD-converting a high frequency narrow-band signal with higher precision and lower power consumption which is provided in an analog front-end of a receiver such as a radio LAN or a portable telephone, and a digital radio receiver using the same band-pass ΔΣ AD modulator.
2. Description of the Prior Art
The use of a band-pass ΔΣ AD modulator has been examined for AD-converting a high frequency narrow-band signal with higher precision and lower power consumption which is provided in an analog front-end of a receiver such as a radio LAN or a portable telephone (See first to sixth non-patent documents described later, for example).
Prior art documents related to the present invention are as follows:
(1) first patent document: Japanese patent laid-open publication No. JP-2000-244323-A;
(2) second patent document: Japanese patent laid-open publication No. JP-2002-100992-A;
(3) first non-patent document: F. Munoz et al., “A 4.7 mW 89.5 dB DR CT Complex ΔΣ ADC with Built-in LPF”, ISSCC Digest of Technical Papers, Vol. 47, pp. 500–501, February 2005;
(4) second non-patent document: R. Schreier et al., “A 10–300 MHz IF-digitizing IC with 90–105-d B dynamic range and 15–333-kHz band width”, IEEE Journal of Solid-State Circuits, Vol. 37 No 12, pp. 1636–1644, December 2002;
(5) third non-patent document: T. Salo et al., “A Dual-Mode 80 MHz Bandpass ΔΣ Modulator for a GSM/WCDMA IF-receiver”, ISSCC Digest of Technical Papers, Vol. 45, pp. 218–219, February 2002;
(6) fourth non-patent document: U. V. Kack et al., “Direct RF Sampling continuous-Time Bandpass ΔΣ A/D Converter Design for 3G Wireless Applications”, Proceedings of IEEE ISCA, pp. I-409–J-412, Vancouver, Canada, May 2004;
(7) fifth non-patent document: P. Fontaine et al., “A Low-Noise Low-Voltage CT ΔΣ Modulator with Digital Compensation of Excess Loop Delay”, ISSCC Digest of Technical Papers, Vol. 47, pp. 498–499, February 2004;
(8) sixth non-patent document: H. San et al., “A noise-shaping algorithm of multi-bit DAC nonlinearities in complex bandpass ΔΣ AD modulators”, IEICE Transactions on Fundamentals, Vol. E87-A, N. 4, pp. 792–800, April 2004;
(9) seventh non-patent document S. R. Norsworthy et al. (editors), “Delta-Sigma Data Converters,-Theory, Design and Simulation”, IEEE Press, pp. 244–245, 1997;
(10) eighth non-patent document: S. Luschs et al., “Radio Frequency Digital-to-Analog Converter”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 9, pp. 1462–1467, September 2004; and
(11) ninth non-patent document: H. Kobayashi et al., “Sampling Jitter and Finite Aperture Time Effects in Wideband Data Acquisition Systems”, IEICE Transactions on Fundamentals, Vol. E85-A, No. 2, pp. 335–346, February 2002.
Various kind of examinations have been made for realizing a software radio system according to a prior art having a minimum-analog and rich-digital circuit configuration, from which a frequency converter circuit for converting an RF signal into a baseband is eliminated so as to directly AD-convert the RF signal (See FIG. 1A). A digital radio receiver according to the prior art of FIG. 1A is constituted by including an antenna 1, a band-pass filter 2, a low-noise amplifier 3, a frequency converter unit 4 for converting an inputted signal into a baseband, a pair of low-pass ΔΣ AD modulators 5a and 5b, and a digital signal processor (DSP) 6. In all the drawings including FIG. 1A and being subsequent to FIG. 1A, an AD converter (analog-to-digital converter) will be abbreviated as an ADC, and a DA converter (digital-to-analog converter) will be abbreviated as a DAC.
Referring to FIG. 1A, conventionally, a configuration of a discrete-time circuit (FIG. 3) has been often used which utilizes a switched capacitor circuit capable of performing AD conversion with higher precision. However, recently, a configuration of a continuous-time circuit (FIG. 4) is studied which utilizes a continuous-time analog filter in the continuous-time circuit, because of the possibility of the operation at a higher rate and with lower power consumption. In this case, an influence of a clock jitter of the internal AD converter is relatively small because of noise-shaping, however, such a problem occurs that an influence of a jitter of an internal DA converter leads to deterioration in precision of the entire AD modulator.